The difference between forever and always is that always can exist as a "module item", which is the name that the Verilog spec gives to constructs that may be written directly within a module, not contained within some other construct. initial is also a module item. always blocks are repeated, whereas initial blocks are run once at the start of ...
The always construct can be used at the module level to create a procedural block that is always triggered. Typically it is followed by an event control, e.g., you might write, within a module, something like: always @(posedge clk)
The (*) means "build the sensitivity list for me". For example, if you had a statement a = b + c; then you'd want a to change every time either b or c changes. In other words, a is "sensitive" to b & c. So to set this up: always @( b or c ) begin a = b + c; end But imagine you had a large always block that was sensitive to loads of signals. Writing the sensitivity list would take ages. In fact ...
verilog - What does always block @ (*) means? - Stack Overflow
The always @() block is sensitive to change of the values all the variables, that is read by always block or we can say which are at the right side inside the always block. In your example, there are no any variables used inside always block, so this always @() block will not work here. As per SV LRM, always_comb is sensitive to changes within the contents of a function, whereas always @* is ...